1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. In particular, the present invention relates to a MISFET which constituting a semiconductor integrated circuit improved in integration.
2. Description of the Related Art
With a view to minimize the sub-threshold current and junction capacity in a complementary MOS (hereinafter referred to as CMOS) transistor, there has been proposed a CMOS transistor of offset gate structure. With this CMOS transistor, it is possible to realize a high speed operation with low power consumption.
Further, with a view to increase the ON current of a thin film transistor and to minimize the leak current thereof, there has been proposed to implant ions in an insulating film of an offset region to bury a negative charge, thus reversing the offset portion. It is also known that the Ion/Ioff ratio of a thin film transistor can be increased by regulating the magnitude of offset to the range of 100 to 200 μm.
In the meantime, it is also proposed to avoid the offset between the gate electrode and the source/drain impurity diffusion region in order to prevent any decrease of the Ion.
In recent years, there has been proposed, with a view to improve the sub-threshold characteristics, to regulate the distance of the offset region between the gate electrode and the impurity diffusion region to the range of 0 to 10 nm.
It is also reported, as a result of studies using a simulation which is aimed at promoting the miniaturization of semiconductor device, that when the impurity diffusion layer is formed of a box-like impurity distribution, it is possible to prevent the reduction of Ion while suppressing any increase of Ioff even if the overlap region formed below the gate of so-called source/drain extension is eliminated therefrom.
In the semiconductor devices of recent years, the gate length thereof is getting shorter, e.g. 40 nm or less as the miniaturization of semiconductor device is further promoted in recent years. When the gate length is extremely short as described above, Ioff is caused to increase due to a strong short channel effect, and when it is tried to suppress this increase of Ioff, Ion is also caused to decrease. Any of the aforementioned offset gate structure and the structure where the source/drain are not overlapped with the gate are not suited for use in an extremely miniaturized MOSFET.